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GALVANTECH, INC. SYNCHRONOUS BURST SRAM
FEATURES
* * * * * * * * * * * * * * Fast access times: 8, 9, 10, and 12ns Fast clock speed: 83, 66, and 50 MHz Provide high performance 2-1-1-1 access rate Fast OE# access times: 5 and 6ns Single +5V +5% power supply 3.3V I/O compatible Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs Byte writeable via dual write enables Address, data and control registers Internally self-timed WRITE CYCLE Automatic power-down for low power applications High board density 52-lead PLCC packages
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
64K x 18 SRAM
+5V SUPPLY WITH CLOCKED, REGISTERED INPUTS, BURST COUNTER
GENERAL DESCRIPTION
The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced double-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The GVT7164B19 SRAM integrates 65,536 x18 SRAM cells with advanced synchronous peripheral circuitry and a 2bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edgetriggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE#), burst control inputs (ADSC#, ADSP#, and ADV#), and write enables (WEL# and WEH#). Asynchronous input includes the output enable (OE#). The data outputs (DQ), enabled by OE#, are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address, data inputs, and write controls are registered onchip to initiate self-timed WRITE cycle. WRITE cycles can be one or two bytes wide as controlled by the write control inputs. Individual byte enables allow individual bytes to be written. WEL# controls DQ1-DQ8 and DQP1. WEH# controls DQ9-DQ16 and DQP2. The GVT7164B19 operates from a +5V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, PentiumTM, 680x0, and for systems that are benefited from a wide synchronous data bus.
OPTIONS
Timing 8ns access/12ns cycle 9ns access/15ns cycle 10ns access/15ns cycle 12ns access/20ns cycle Packages 52-pin PLCC
MARKING
-8 -9 -10 -12 C
*
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699
Rev. 12/97
Pentium is a trademark of Intel Corporation. Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
UPPER BYTE WRITE
WEH# CLK
D
Q
LOWER BYTE WRITE
WEL#
D
Q
lo byte write hi byte write Output Buffers
ENABLE
CE#
D
Q
OE# ADSP# Input Register A15-A2 ADSC# CLR ADV# A1-A0 Binary Counter & Logic
Address Register 64K x 9 x 2 SRAM Array
DQ1-DQ16 DQP1 DQP2
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
PIN ASSIGNMENT (Top View)
DQ9 DQ10 VCC VSS DQ11 DQ12 DQ13 DQ14 VSS VCC DQ15 DQ16 DQP2
A6 A7 CE# WEH# WEL# ADSC# ADSP# ADV# CLK OE# A8 A9 A10
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41
52-pin PLCC
40 39 38 37 36 35 34
DQP1 DQ8 DQ7 VCC VSS DQ6 DQ5 DQ4 DQ3 VSS VCC DQ2 DQ1
December 4, 1997
Rev. 12/97
A5 A4 A3 A2 A1 A0 VSS VCC A15 A14 A13 A12 A11
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Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
PIN DESCRIPTIONS
PLCC PINS
26, 25, 24, 23, 22, 21, 7, 6, 49, 48, 47, 33, 32, 31, 30, 29 3,4
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
SYMBOL
A0-A15
TYPE
Input-
DESCRIPTION
Addresses: These inputs are registered and must meet the setup and hold times around the Synchronous rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. InputByte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ are high impedance if either of these inputs are LOW.
Synchronous cycle. WEL# controls DQ1-DQ8 and DQP1. WEH# controls DQ9-DQ16 and DQP2. Data I/O
WEL#, WEH# CLK
51
Input-
Clock: This signal registers the addresses, data, chip enables, write control and burst control clock's rising edge.
Synchronous inputs on its rising edge. All synchronous inputs must meet setup and hold times around the
5 50 52 1 2
CE# OE# ADV# ADSP# ADSC#
InputSynchronous
Chip Enable: This active LOW input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH Address Status Processor: This active LOW input causes a new external address to be Address Status Controller: This active LOW input causes device to be de-selected or selected depending upon write control inputs.
Input InputInputInput-
Synchronous on this pin generates wait cycle (no address advance). Synchronous registered and a READ cycle is initiated using the new address. Synchronous along with new external address to be registered. A READ or WRITE cycle is initiated
34, 35, 38, 39, 40, 41, 44, 45, 8, 9, 12, 13, 14, 15, 18, 19 46, 20 10, 17, 28, 36, 43 11, 16, 27, 37, 42
DQ1-DQ16
Input/ Output Input/ Output Supply Ground
Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9-DQ16. Input data must meet setup and hold times around the rising edge of CLK. Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9-DQ16. Supply: +5V + 5% Ground: GND
DQP1, DQP2 VCC VSS
BURST ADDRESS TABLE
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A00 A...A11 A...A10
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A10 A...A01 A...A00
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
TRUTH TABLE
OPERATION ADDRESS USED CE#
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
ADSP# ADSC#
ADV#
WRITE#
OE#
CLK
DQ
Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst
None None External External External External External Next Next Next Current Current Current
H H L L L L L X X X X X X
X L L L H H H H H H H H H
L X X X L L L H H H H H H
X X X X X X X L L L H H H
X X X X L H H H H L H H L
X X L H X L H L H X L H X
L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
High-Z High-Z Q High-Z D Q High-Z Q High-Z D Q High-Z D
Note:
1. 2. 3. 4. 5. 6. 7.
X means "don't care." H means logic HIGH. L means logic LOW. WRITE# = L means WEL#*WEH# equals LOW. WRITE# = H means WEL#*WEH# equals HIGH. WEL# enables write to DQ1-DQ8 and DQP1. WEH# enables write to DQ9-DQ16 and DQP2. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. Suspending burst generates wait cycle. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE FOR READ/WRITE
FUNCTION READ WRITE high byte WRITE low byte WRITE all bytes WEH# H L H L WEL# H H L L CE# L L L L OE# L X X X
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V VIN ...........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) .........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ...........................................................1.6W Short Circuit Output Current ..........................................30mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0oC Ta
70C; VCC = 5V +5% unless otherwise noted)
CONDITIONS SYMBOL
VIH VIl 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA ILI ILO VOH VOL VCC 4.75
DESCRIPTION
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage
MIN
2.2 -0.5 -2 -2 2.4
MAX
VCC+0.3 0.8 2 2 3.3 0.4 5.25
UNITS
V V uA uA V V V
NOTES
1,2 1, 2
1, 11 1, 11 1
DESCRIPTION
Power Supply Current: Operating CMOS Standby
CONDITIONS
Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open Device deselected; VCC = MAX; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH ; all inputs static; VCC = MAX; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN
SYM
Icc
TYP
200
-8
300
-9
275
-10
265
-12
250
UNITS NOTES
mA 3, 12, 13
ISB2
5
12
12
12
12
mA
12,13
TTL Standby
ISB3
15
35
35
35
35
mA
12,13
Clock Running
ISB4
30
60
50
50
40
mA
12,13
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 5.0V
SYMBOL
CI CO
TYP
4 6
MAX
5 8
UNITS
pF pF
NOTES
4 4
THERMAL CONSIDERATION
DESCRIPTION
Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case
CONDITIONS
Still air, soldered on 4.25 x 1.125 inch 4-layer PCB
SYMBOL
JA JC
PLCC TYP
TBD 3
UNITS
oC/W oC/W
NOTES
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0oC
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
TA 70oC; VCC = 5.0V +5 %)
SYM
tKC tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tS tH
DESCRIPTION
Clock Clock cycle time Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address, Controls and Data In Hold Times Address, Controls and Data In
-8
MIN MAX MIN
-9
MAX MIN
-10
MAX MIN
-12
MAN UNITS NOTES
12 4 4 8 3 5 5 5 0 5 2.5 0.5
15 5 5 9 3 6 5 5 0 5 2.5 0.5
15 5 5 10 3 6 5 5 0 5 2.5 0.5
20 6 6 12 3 6 6 6 0 6 3 0.5
ns ns ns ns ns ns ns ns ns ns ns ns 6,7 6,7 9 6,7 6,7 10 10
CAPACITANCE DERATING
DESCRIPTION
Clock to output valid
SYMBOL
tKQ
TYP
0.016
MAX
UNITS
ns / pF
NOTES
14
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
OUTPUT LOADS
Q Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT +5V 480 Q 255 5 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. 8. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t tKC /2. VIL -2.0V for t tKC /2
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. OE# is a "don't care" when a byte write enable is sampled LOW.
9.
10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11. AC I/O curves are available upon request. 12. "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13. Typical values are measured at 5.0V, 25oC and 20ns cycle time. 14. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
tKC t
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
READ TIMING
KL
CLK
t
S
t
KH
ADSP#
t
H
ADSC#
t
S
ADDRESS
A1
t
A2
H
WEH#, WEL#
CE#
t
S
ADV#
t
H
OE#
tKQ tKQLZ tOELZ t
OEQ Q(A2)
tKQ
DQ
Q(A1)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A2+2)
SINGLE READ
BURST READ
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
CLK
tS
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
WRITE TIMING
ADSP#
tH
ADSC#
tS
ADDRESS
A1
tH
A2
A3
WEH#, WEL#
CE#
tS
ADV#
tH
OE#
tOEHZ tKQX
DQ
Q
D(A1)
D(A2)
D(A2+2)
D(A2+2)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
CLK
tS
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
READ/WRITE TIMING
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
tH
A3
A4
A5
WEH#, WEL#
CE#
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3) Single Write
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single Reads
Burst Read
Burst Write
December 4, 1997
11
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
52 Pin PLCC Package Dimensions
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
.795 (20.19) .785 (19.94) .756 (19.20) .750 (19.05)
.050 (1.27) TYP
.795 (20.19) .785 (19.94)
.756 (19.20) .750 (19.05)
.600 (15.24) TYP .045 (1.14) X 45 o TYP
PIN #1 INDEX
.795 (20.19) .785 (19.94)
.180 (4.57) .165 (4.19)
.120 (3.05) .090 (2.29) .021 (0.53) .013 (0.33) .730 (18.54) .690 (17.53) .020 (0.51) MIN
Note: All dimensions in inches (millimeters)
MAX MIN
or typical where noted.
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97
GALVANTECH, INC.
Ordering Information
GVT7164B19 64K X 18 SYNCHRONOUS BURST SRAM
GVT 7164B19 X - XX
Galvantech Prefix Part Number Speed (8 = 8ns access/12ns cycle 9 = 9ns access/15ns cycle 10 = 10ns access/15ns cycle 12 = 12ns access/20ns cycle) Package (C = 52 PIN PLCC)
December 4, 1997
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 12/97

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